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Claude Skills by chipweaver
github.com/chipweaver12 skills0 installs17 views
- BrainstormUse when brainstorming a new module's requirements and architecture into a brainstorm.md, one way to write the intent document the pipeline starts from; not for design.md, RTL, constraints, or any in-pipeline stage.Votes: 0GitHub stars: 6
- Design FlowUse when progressing IC design through stages, checking module status, or routing rework decisions; not for single-stage execution or artifact authoring.Votes: 0GitHub stars: 6
- Env PrecheckUse when checking whether this machine's Python, EDA tools and licenses can actually run VeriPower's stages; not for any pipeline stage, module state, or design work.Votes: 0GitHub stars: 6
- Lint CdcCheck RTL lint and clock-domain crossings with SpyGlass, evaluate violations and justified waivers, and close the current assessment.Votes: 0GitHub stars: 6
- Power AnalysisBuild and check power experiments, calculate averaged gate-level power with SAIF and PT-PX, and assess the results against the task's power requirements; not for functional regression or static timing analysis.Votes: 0GitHub stars: 6
- Rtl DesignUse when writing or modifying RTL and its file/constraint annotations, reviewing implementation against requirements, or repairing an implementation defect; not for running synthesis or functional regression as a pipeline stage.Votes: 0GitHub stars: 6
- Simulation PlanUse when generating or evolving a module's verification strategy, testpoints, TB scaffold and power measurement plan; not for implementing the testbench or running a regression.Votes: 0GitHub stars: 6
- Simulation TriageDiagnose a failed verification run from requirements, implementation and experimental evidence, and identify the repair owner; not for editing canonical design or verification artifacts.Votes: 0GitHub stars: 6
- SimulationImplement, review and run a module's functional testbench, diagnose verification failures and assess coverage; not for changing upstream RTL or requirements.Votes: 0GitHub stars: 6
- SpecificationEstablish requirements, design decisions, interfaces, clocks and constraints from the delivered intent, or revise them after evidence-based clarification; not for implementing RTL or verification.Votes: 0GitHub stars: 6
- SynthesisEstablish the synthesized implementation, its constraints and measurements, and assess them against the task's requirements.Votes: 0GitHub stars: 6
- Timing AnalysisAssess post-synthesis setup and hold timing with PrimeTime and determine what the evidence establishes under the task's constraints.Votes: 0GitHub stars: 6