Semi Reference

---
name: semi-reference
description: "Use when correcting a semiconductor misconception, looking up a node, wafer, yield, defect-density, mask or cost figure, finding the sources, or needing a quick-reference picker — plus the current state of High-NA lithography adoption and advanced packaging as the binding constraint. Companion to the other semiconductor skills."
---

# Semiconductors and Chip Manufacturing: What's Live, Misconceptions, Numbers, and Sources

> **Part 6 of 6** of the *Semiconductors and Chip Manufacturing* reference (plugin `semiconductors-and-chip-manufacturing`), covering §27–§32. Sibling skills: `semi-carriers-doping-junctions-mosfet-and-scaling` (§0–§5), `semi-transistor-architectures-interconnect-memory-and-wafers` (§6–§9), `semi-cleanroom-lithography-deposition-etch-and-cmp` (§10–§15), `semi-integration-yield-metrology-test-and-packaging` (§16–§20), `semi-pcb-assembly-reliability-design-flow-and-economics` (§21–§26). Section numbers are shared across the set; a reference written as §N → `skill` points into that sibling skill.
>
> **Currency:** The physics is settled. Two frontiers are moving. See §27 for High-NA lithography adoption, and advanced packaging as the binding constraint.

> **⚠️ The most complex manufacturing humans do, by a wide margin.** ⚠️ **A leading-edge
> chip involves on the order of a thousand process steps, features smaller than a virus,
> tolerances measured in atoms, and a supply chain with genuine single points of failure.**
>
> **Builds directly on an electromagnetism reference (band theory, pn junctions, MOSFET
> physics, wide-bandgap materials). Complements a manufacturing reference (tolerancing and
> yield), an organic-chemistry reference (photoresists and packaging polymers), and a
> resource-extraction reference (where the materials come from).**
>
> **⚠️ GOTCHA** boxes mark where marketing and physics diverge — and this industry has more
> of that gap than most.
>
> **The three ideas that organize this document:**
> 1. **⚠️ "NODE NAMES ARE MARKETING"** (§5 → `semi-carriers-doping-junctions-mosfet-and-scaling`). **"3nm" does not describe any physical
>    dimension on the chip. It has been a marketing label for roughly a decade, and
>    comparing nodes across foundries by name is meaningless.**
> 2. **⚠️ YIELD IS THE WHOLE BUSINESS** (§17 → `semi-integration-yield-metrology-test-and-packaging`). **Everything — die size, chiplet
>    architecture, defect control, cleanroom spend — is downstream of the fact that
>    profitability is set by what fraction of die work.**
> 3. **⚠️ THE BOTTLENECK MOVED TO THE BACK END** (§20 → `semi-integration-yield-metrology-test-and-packaging`, §27.2). **For AI accelerators the
>    binding constraint is no longer transistors — it is packaging and memory, which is a
>    genuine reversal of thirty years of industry structure.**

---

## §27. What's Live — checked August 2026

### 27.1 ⚠️ High-NA EUV: in production, and the leaders disagree about it
**⚠️ §11 → `semi-cleanroom-lithography-deposition-etch-and-cmp`'s frontier, and it has just crossed from R&D into manufacturing — with a genuine
split between foundries about whether it is worth the money.**

- **⚠️ THE TOOL.** ⚠️ **ASML's TWINSCAN EXE:5200B, with 0.55 NA anamorphic optics from Zeiss,
  at a reported cost of roughly $360–400 million per machine.** ⚠️ **Intel reported the
  EXE:5200B at 175 wafers per hour with 0.7 nm overlay.** ⚠️ **Standard 0.33-NA EUV tops out
  around 13 nm half-pitch in a single exposure; High-NA reportedly enables features up to
  66% smaller.**
- **⚠️ IT IS NOW IN VOLUME PRODUCTION.** ⚠️ **Intel installed the industry's first
  commercial High-NA tool in December 2025, and on 15 July 2026 ASML confirmed High-NA EUV
  had reached high-volume manufacturing — used to pattern specific layers of Intel Core
  Ultra Series 3 (Panther Lake) processors built on Intel 18A.**
- ⚠️ **Note the nuance that coverage sometimes loses: 18A was DESIGNED around Low-NA EUV
  and multi-patterning and does not depend on High-NA to ship.** ⚠️ **18A is the commercial
  validation; Intel's 14A is the node where High-NA becomes foundational.**
- **⚠️ Samsung and SK hynix are also adopting** — ⚠️ **Samsung reportedly received its first
  EXE:5200B in late 2025 with a second in H1 2026 for advanced foundry lines, and SK hynix
  is reported as the first memory maker to install a commercial system.**

> **⚠️ GOTCHA — TSMC, the largest foundry, is deliberately SITTING OUT, and its reasoning is
> economically serious rather than conservative.** ⚠️ **TSMC has said High-NA remains too
> expensive at this stage and plans to continue using current EUV systems for the next
> several chip generations — with A13 and A12, targeted for 2029, reportedly not requiring
> High-NA.**
> ⚠️ **The underlying argument: existing Low-NA tools can match High-NA's resolution using
> DOUBLE PATTERNING, and one analysis estimates that approach may still cost LESS than
> High-NA single patterning.** ⚠️ **Against that, each extra patterning step reportedly adds
> a mask set, alignment error budget, two more etch steps and roughly 30% to wafer cost —
> and by the 2nm node the most aggressive layers were already triple- and
> quadruple-patterned.**
> **⚠️ So this is a genuine open question about where the crossover sits, not a case of one
> party being wrong.** ⚠️ **ASML's own CEO frames adoption as gradual, with high-volume
> manufacturing expected across 2027–28.**

**⚠️ Hyper-NA** is reported as ASML's next step, some time in the next decade.
**⚠️ Sourcing note: ASML and Intel are interested parties on one side and TSMC on the
other; I've taken the production milestone from ASML's own press release and the
cost-benefit dispute from trade reporting on both companies' statements.**

### 27.2 ⚠️ The bottleneck moved to packaging and memory
**⚠️ §20 → `semi-integration-yield-metrology-test-and-packaging`'s subject becoming the industry's binding constraint — and this is a genuine
reversal of decades of structure.**

- **⚠️ THE CLARIFYING NUMBER.** ⚠️ **Epoch AI estimates the four largest AI chip designers
  collectively consumed around 90% of global CoWoS capacity and HBM supply in 2025 — while
  consuming only about 12% of advanced LOGIC DIE production.**
  ⚠️ **That single comparison tells you where the constraint is: not transistors.**
- **⚠️ WHY.** ⚠️ **An AI accelerator cannot be a single monolithic die — reticle limits
  (§17 → `semi-integration-yield-metrology-test-and-packaging`) and yield force chiplets, and the compute die must sit adjacent to multiple HBM
  stacks on an interposer.** ⚠️ **So every accelerator needs a front-end wafer AND a CoWoS
  slot AND an HBM allocation, and no single intervention resolves it.**
- **⚠️ CAPACITY IS SCALING FAST AND STILL SHORT.** ⚠️ **Reported figures vary by source and
  by what they count, but the direction is consistent: TSMC CoWoS capacity has roughly
  tripled since 2023, with 2026 in-house targets reported variously around 120,000–140,000
  wafers per month, plus OSAT spillover.** ⚠️ **TrendForce is cited estimating the
  supply-demand gap narrowing from around 20% to around 10% by end-2026.**
  ⚠️ **CoWoS is reported fully booked, with NVIDIA holding roughly 60% of allocation.**
- **⚠️ HBM IS THE CO-EQUAL CONSTRAINT.** ⚠️ **HBM3E reportedly effectively sold out for 2026;
  HBM4 ramping into late 2026.** ⚠️ **A structural problem underneath: HBM4 is reported to
  need roughly 3× the wafer area of standard DRAM for the same capacity, so reallocating
  fabs toward HBM tightens conventional DRAM — which is why memory prices for ordinary PCs
  rose.** ⚠️ **HBM is reported at around 25% of DRAM industry revenue on under 5% of bit
  volume.**

> **⚠️ GOTCHA — capacity announcements are a LAGGING indicator, because capacity that cannot
> pass customer qualification does not ship.** ⚠️ **Reporting on Samsung's 12-layer HBM3E
> stacking yield difficulties makes the point: stacking more dies compresses bonding
> alignment tolerance and TSV integrity margins, so an announced capacity increase is only
> meaningful once yield is proven.**
> ⚠️ **This is §17 → `semi-integration-yield-metrology-test-and-packaging`'s yield lesson reappearing at the package level — and it is why HYBRID
> BONDING (§20 → `semi-integration-yield-metrology-test-and-packaging`) is described as becoming essential rather than optional.**

**⚠️ Where this is heading**: ⚠️ **reporting points to CoWoS generations supporting eight
HBM4 stacks with dual compute chiplets, 16-high stacks raising yield and thermal risk, and
CO-PACKAGED OPTICS moving into high-performance systems as power savings in AI networking
become compelling.** ⚠️ **One analysis notes memory and packaging together now represent
60–70% of AI accelerator cost of goods — logic silicon is no longer the dominant cost,
which is the whole story in one line.**
**⚠️ Sourcing caution: capacity and share figures here come from market-intelligence firms
and supply-chain consultancies and DISAGREE with each other on specifics — I've reported
ranges and marked them.** ⚠️ **The Epoch AI 90%/12% comparison is the most useful and
best-sourced single datum, and it is an estimate.**

---

## §28. Misconceptions

| Misconception | Correction |
|---|---|
| "3nm" is a physical dimension | ⚠️ **A marketing name since ~22nm. Compare density instead** (§5 → `semi-carriers-doping-junctions-mosfet-and-scaling`) |
| Moore's Law is a law of physics | ⚠️ **An economic observation about cost per transistor** (§5 → `semi-carriers-doping-junctions-mosfet-and-scaling`) |
| Moore's Law ended | ⚠️ **Density still rises; DENNARD scaling ended, and cost/transistor stalled** (§5 → `semi-carriers-doping-junctions-mosfet-and-scaling`) |
| Multicore happened because parallel is better | ⚠️ **Frequency scaling stopped. It was forced** (§5 → `semi-carriers-doping-junctions-mosfet-and-scaling`) |
| Voltage can keep scaling down | ⚠️ **60 mV/decade subthreshold floor blocks it** (§4 → `semi-carriers-doping-junctions-mosfet-and-scaling`, §5 → `semi-carriers-doping-junctions-mosfet-and-scaling`) |
| Transistors are the speed limit | ⚠️ **Interconnect RC dominates at the leading edge** (§7 → `semi-transistor-architectures-interconnect-memory-and-wafers`) |
| SRAM shrinks with logic | ⚠️ **It has scaled poorly, which drives chiplet partitioning** (§8 → `semi-transistor-architectures-interconnect-memory-and-wafers`) |
| EUV is just a shorter wavelength | ⚠️ **Everything absorbs it — vacuum, all-reflective optics, tin plasma** (§11 → `semi-cleanroom-lithography-deposition-etch-and-cmp`) |
| Bigger chips are better | ⚠️ **Yield falls exponentially with area** (§17 → `semi-integration-yield-metrology-test-and-packaging`) |
| Chiplets are about modularity | ⚠️ **Primarily yield and the reticle limit** (§17 → `semi-integration-yield-metrology-test-and-packaging`, §20 → `semi-integration-yield-metrology-test-and-packaging`) |
| Chiplets are strictly cheaper | ⚠️ **Known-good-die testing adds 15–30% test cost** (§19 → `semi-integration-yield-metrology-test-and-packaging`) |
| Packaging is an afterthought | ⚠️ **It's the binding constraint for AI silicon** (§20 → `semi-integration-yield-metrology-test-and-packaging`, §27.2) |
| A fab's cost is the building | ⚠️ **Tools. One EUV scanner is hundreds of millions** (§25 → `semi-pcb-assembly-reliability-design-flow-and-economics`, §27.1) |
| Chips are made where they're designed | ⚠️ **Fabless/foundry split; leading edge is concentrated** (§25 → `semi-pcb-assembly-reliability-design-flow-and-economics`, §26 → `semi-pcb-assembly-reliability-design-flow-and-economics`) |
| The leading edge is most of the industry | ⚠️ **Most chips by unit come from mature nodes** (§25 → `semi-pcb-assembly-reliability-design-flow-and-economics`) |
| Copper is etched like aluminium | ⚠️ **It isn't — hence damascene and CMP** (§13 → `semi-cleanroom-lithography-deposition-etch-and-cmp`, §15 → `semi-cleanroom-lithography-deposition-etch-and-cmp`) |
| Annealing is straightforward heating | ⚠️ **Thermal budget: heat activates AND diffuses** (§14 → `semi-cleanroom-lithography-deposition-etch-and-cmp`) |
| Dummy metal fill is wasted area | ⚠️ **CMP density rules require it** (§15 → `semi-cleanroom-lithography-deposition-etch-and-cmp`) |
| A chip either works or doesn't | ⚠️ **Binning monetizes partial failures** (§17 → `semi-integration-yield-metrology-test-and-packaging`) |
| Overclocking only risks crashes | ⚠️ **It consumes rated lifetime — TDDB, electromigration** (§23 → `semi-pcb-assembly-reliability-design-flow-and-economics`) |
| Memory bit flips are defects | ⚠️ **Cosmic rays and alphas. Hence ECC** (§23 → `semi-pcb-assembly-reliability-design-flow-and-economics`) |
| FR-4 is fine for any board | ⚠️ **Its loss tangent destroys multi-GHz signals** (§21 → `semi-pcb-assembly-reliability-design-flow-and-economics`) |
| Lead-free solder was a pure improvement | ⚠️ **Higher melting, narrower window, tin whiskers** (§22 → `semi-pcb-assembly-reliability-design-flow-and-economics`) |
| High-NA EUV is obviously the next step | ⚠️ **TSMC is sitting it out on cost grounds** (§27.1) |
| AI chips are limited by logic wafers | ⚠️ **~90% of CoWoS and HBM vs ~12% of logic dies** (§27.2) |
| Announced HBM capacity means supply | ⚠️ **Capacity that fails qualification doesn't ship** (§27.2) |

---

## §29. Numbers

```
⚠️ Subthreshold swing floor  ⚠️ ~60 mV/decade at room temperature
⚠️ Silicon bandgap  ~1.1 eV · ⚠️ EG silicon purity ~11 nines
⚠️ Wafer  300 mm standard · ⚠️ 450 mm abandoned
⚠️ Yield  ⚠️ Y ≈ e^(−AD) — falls EXPONENTIALLY with die area
⚠️ EUV wavelength  13.5 nm · ⚠️ Low-NA 0.33 · High-NA 0.55
⚠️ Low-NA single-exposure limit  ⚠️ ~13 nm half-pitch
⚠️ High-NA tool  ⚠️ ~$360–400m · EXE:5200B 175 wph, 0.7 nm overlay
⚠️ Extra patterning step  ⚠️ reportedly ~+30% wafer cost
⚠️ High-NA in HVM  ⚠️ 15 July 2026 (Intel 18A / Panther Lake)
⚠️ AI designers' share  ⚠️ ~90% of CoWoS and HBM · ~12% of logic dies
⚠️ TSMC CoWoS  ⚠️ ~3× since 2023; 2026 targets ~120–140k wpm (reported)
⚠️ CoWoS gap  ⚠️ ~20% → ~10% by end-2026 (TrendForce, reported)
⚠️ HBM4 wafer area  ⚠️ ~3× standard DRAM for same capacity (reported)
⚠️ HBM share of DRAM revenue  ⚠️ ~25% on <5% of bits (reported)
⚠️ Memory + packaging  ⚠️ ~60–70% of AI accelerator COGS (reported)
⚠️ Chiplet test premium  ⚠️ ~15–30% over monolithic (reported)
```

---

## §30. Sources

| Source | Why |
|---|---|
| **Sze & Ng, *Physics of Semiconductor Devices*** | ⚠️ **The device physics standard** |
| **Streetman & Banerjee, *Solid State Electronic Devices*** | More accessible entry |
| **Plummer, Deal & Griffin, *Silicon VLSI Technology*** | ⚠️ **Process integration** |
| **May & Spanos, *Fundamentals of Semiconductor Manufacturing*** | ⚠️ **§16–§18 → `semi-integration-yield-metrology-test-and-packaging`, yield and control** |
| **Weste & Harris, *CMOS VLSI Design*** | ⚠️ **§24 → `semi-pcb-assembly-reliability-design-flow-and-economics`, the design side** |
| **Lau, *Semiconductor Advanced Packaging*** | ⚠️ **§20 → `semi-integration-yield-metrology-test-and-packaging`** |
| **IPC standards (2221, 6012, A-610)** | ⚠️ **§21–§22 → `semi-pcb-assembly-reliability-design-flow-and-economics`, the actual rules** |
| **imec and SEMI publications** | ⚠️ **Roadmaps from non-vendors** |
| **ASML, TSMC and Intel technical disclosures** | ⚠️ **Primary — and read as interested parties** |
| **SemiAnalysis, TechInsights, Epoch AI** | ⚠️ **§27 — paywalled but the serious analysis** |
| **Miller, *Chip War*** | ⚠️ **§26 → `semi-pcb-assembly-reliability-design-flow-and-economics`'s geopolitics, readable** |

---

## §31. Quick Reference

### 31.1 Picker
| Question | Where |
|---|---|
| Is "3nm" better than "4nm"? | ⚠️ **Meaningless across foundries. Compare density** (§5 → `semi-carriers-doping-junctions-mosfet-and-scaling`) |
| Why did clock speeds stop rising? | ⚠️ **Dennard scaling ended; voltage couldn't follow** (§5 → `semi-carriers-doping-junctions-mosfet-and-scaling`) |
| Why so many specialized accelerators? | ⚠️ **Dark silicon — you can't power it all** (§5 → `semi-carriers-doping-junctions-mosfet-and-scaling`) |
| Why chiplets? | ⚠️ **Yield vs area, plus the reticle limit** (§17 → `semi-integration-yield-metrology-test-and-packaging`, §20 → `semi-integration-yield-metrology-test-and-packaging`) |
| Why is my big die so expensive? | ⚠️ **Exponential yield loss** (§17 → `semi-integration-yield-metrology-test-and-packaging`) |
| Why does EUV cost so much? | ⚠️ **Vacuum, reflective optics, tin plasma, one supplier** (§11 → `semi-cleanroom-lithography-deposition-etch-and-cmp`, §26 → `semi-pcb-assembly-reliability-design-flow-and-economics`) |
| Where's the AI hardware bottleneck? | ⚠️ **Packaging and HBM, not logic** (§27.2) |
| Should we design for the leading node? | ⚠️ **Mask cost sets minimum volume** (§16 → `semi-integration-yield-metrology-test-and-packaging`, §25 → `semi-pcb-assembly-reliability-design-flow-and-economics`) |
| Why does the board material matter? | ⚠️ **Loss tangent and impedance at speed** (§21 → `semi-pcb-assembly-reliability-design-flow-and-economics`) |
| Why did the solder joint crack? | ⚠️ **CTE mismatch under thermal cycling** (§23 → `semi-pcb-assembly-reliability-design-flow-and-economics`) |
| Does running hot matter? | ⚠️ **Arrhenius. It consumes rated life** (§23 → `semi-pcb-assembly-reliability-design-flow-and-economics`) |
| Why does ECC exist? | ⚠️ **Soft errors are physics, not defects** (§23 → `semi-pcb-assembly-reliability-design-flow-and-economics`) |

### 31.2 Design and sourcing checks
- [ ] ⚠️ **Node chosen on density/PPA and mask cost, not on the name** (§5 → `semi-carriers-doping-junctions-mosfet-and-scaling`, §25 → `semi-pcb-assembly-reliability-design-flow-and-economics`)
- [ ] ⚠️ **Die size checked against yield model and reticle limit** (§17 → `semi-integration-yield-metrology-test-and-packaging`)
- [ ] Chiplet partition justified against known-good-die test cost (§19 → `semi-integration-yield-metrology-test-and-packaging`, §20 → `semi-integration-yield-metrology-test-and-packaging`)
- [ ] ⚠️ **Packaging technology and CAPACITY secured, not assumed** (§20 → `semi-integration-yield-metrology-test-and-packaging`, §27.2)
- [ ] HBM or memory allocation confirmed if relevant (§27.2)
- [ ] ⚠️ **Thermal path designed for the package, not just the die** (§20 → `semi-integration-yield-metrology-test-and-packaging`, §23 → `semi-pcb-assembly-reliability-design-flow-and-economics`)
- [ ] DFT coverage adequate and test time budgeted (§19 → `semi-integration-yield-metrology-test-and-packaging`)
- [ ] ⚠️ **DFM and density rules met — dummy fill, hot spots** (§15 → `semi-cleanroom-lithography-deposition-etch-and-cmp`, §17 → `semi-integration-yield-metrology-test-and-packaging`) |
- [ ] Board stack-up: impedance, loss tangent, return paths (§21 → `semi-pcb-assembly-reliability-design-flow-and-economics`)
- [ ] ⚠️ **Reliability targets stated with temperature and voltage** (§23 → `semi-pcb-assembly-reliability-design-flow-and-economics`)
- [ ] ⚠️ **Single-source dependencies identified across the BOM** (§26 → `semi-pcb-assembly-reliability-design-flow-and-economics`)

---

## §32. Method

**§1–§26 → `semi-carriers-doping-junctions-mosfet-and-scaling`, `semi-transistor-architectures-interconnect-memory-and-wafers`, `semi-cleanroom-lithography-deposition-etch-and-cmp`, `semi-integration-yield-metrology-test-and-packaging`, `semi-pcb-assembly-reliability-design-flow-and-economics` rests on settled device physics and mature manufacturing practice** — **MOSFET
operation, the yield model, the lithography ladder, damascene copper, packaging types and
the reliability mechanisms.** ⚠️ **None needed verification; the 60 mV/decade limit is
Boltzmann statistics and Dennard's paper is from 1974.**

**Two searches were run in August 2026**, on **High-NA EUV** and **advanced packaging** —
⚠️ **the first because §11 → `semi-cleanroom-lithography-deposition-etch-and-cmp`'s frontier just moved from R&D into production, the second
because §20 → `semi-integration-yield-metrology-test-and-packaging` has become the industry's binding constraint and that is a structural
reversal.**

**Confidence.** **High** in §5 → `semi-carriers-doping-junctions-mosfet-and-scaling` and §17 → `semi-integration-yield-metrology-test-and-packaging`, which are the sections I'd most want read.
⚠️ **The Dennard-versus-Moore distinction is the single most useful correction here:
"Moore's Law is dead" is wrong in the way people usually mean it, and what actually ended
was Dennard scaling — with the 60 mV/decade subthreshold floor as the specific physical
reason, and multicore and dark silicon as the direct consequences.** ⚠️ **§17 → `semi-integration-yield-metrology-test-and-packaging`'s exponential
yield-versus-area relationship is the second, because it explains chiplets, binning,
product stacks and the reticle limit all at once.** **§5 → `semi-carriers-doping-junctions-mosfet-and-scaling`'s node-naming gotcha is the one
that most often prevents a bad decision.**

**High** on §27.1's production milestone, which comes from ASML's own press release
confirming High-NA reached high-volume manufacturing on Intel 18A on 15 July 2026, and on
the tool specifications reported by Intel.
⚠️ **The genuinely interesting content is the DISAGREEMENT, and I've presented it as an
open economic question rather than picking a winner — TSMC's position that Low-NA double
patterning may still cost less than High-NA single patterning is a serious argument, and
one analysis puts TSMC's likely adoption out around 2029–30.** ⚠️ **Cost figures
($360–400m), the 66% smaller features claim and the ~30% per-patterning-step cost adder are
all from trade reporting and marked as reported.**

**Moderate-to-high** on §27.2, and the confidence is uneven by claim. ⚠️ **The Epoch AI
estimate — roughly 90% of CoWoS and HBM against about 12% of advanced logic dies — is the
best-sourced and most clarifying single datum, and it is explicitly an estimate.**
⚠️ **The capacity numbers are the weak part: sources give TSMC CoWoS 2026 figures ranging
from about 45,000 to 140,000 wafers per month depending on date, scope and whether OSAT is
included, and I have reported the range rather than picking one.** ⚠️ **Most of this
material comes from market-intelligence firms, supply-chain consultancies and investment
outlets with positions, which I've flagged in-section.** **⚠️ The structural claim — that
the constraint has moved from front end to back end — is consistent across every source and
is the part worth carrying.**