Step3 Schematic

---
name: step3-schematic
description: "Step 3 · Schematic design (incl. component selection and BOM)"
disable-model-invocation: true
---

# Step 3 · Schematic design (incl. component selection)

## Session & state check (before touching anything)
1. One step per session: if this session already did substantive work for another step, stop and ask for a fresh session.
2. Read `docs/flow-state.md` (canonical header line; foreign file → stop and ask). Missing → step1 first. Confirm step 2 is `done`; read the pin-map carrier (path in flow-state), `docs/pinmap.md`, `docs/dev-plan.md`. Not satisfied → stop and report.
3. This step already `done` with no issue targeting it → re-run: ask intent first. Already `in-progress` → aborted or concurrent session: ask before proceeding. Marked `rework` → redo what the rework note requires, then wrap up.
4. Issues-table entries with target step = 3 → fix mode.
5. Set step 3 `in-progress`. Rebuild context from disk only.

## Execute

**Adopt-and-audit path**: if flow-state/requirements record an inherited BOM, selection preference, or schematic (`inherited: <path>`), ingest it instead of re-selecting — then audit it per this step's own disciplines: budget-line contributions for every part, ★special-part flags, do-not-substitute identification; *verified-rely-on* parts get spot checks, new and changed parts get the full discipline. ERC and the netlist diff run regardless. **The bar doesn't move; only the labor does.**

**Selection discipline**
- Cheap-first + mainstream mass-production parts; prefer parts your assembly service stocks free of loading/setup fees (e.g. JLC's "basic library"); recompute operating points whenever changing values or library tiers
- With no physical verification available, RF goes on a pre-certified module, never a bare chip with self-routed RF
- Before rejecting a part, verify the rejection's factual claims ("out of stock", "no SPICE model" often collapse under an online check)
- Parameters that cannot be simulated (optics, aging, wear…) ship the vendor's conservative default
- ★Special-part flags, each with a reason: pricey / thin stock / single compatible vendor / critical-path do-not-substitute / self-sourced
- Parts whose datasheet worst-case values underpin the budget/review tables: **no cheap substitution** (swapping the part swaps out the evidence)
- Check every part's contribution to each hard budget line in the plan (current, cost, height, …) line by line; any line over its cap → selection rollback (a part whose contribution cannot be closed at design time gets cut — e.g. an always-powered part with no credible quiescent-current figure)

**Circuit & review**
- Answer every open parameter from the original component/module spec, never from third-party reference boards
- Gated circuits: audit **off-state DC potential node by node**; cross-domain parts: enumerate every power-up/down combination for leakage/backfeed paths
- Verify every pin's reset default state is safe (default-on or default-off?)

**Done criteria**: ERC 0 errors + netlist vs. expected connections **pin-by-pin diff** clean (on EasyEDA: build a geometric netlister — aggregate pin/port/wire coordinates and diff pin by pin against the expected netlist; never call the client-hanging getNetlist()) + BOM with per-part rationale and ★flags.

## Fix mode (entries with target step = 3)
Fix only the listed issues. Each fix: update schematic/BOM → re-run ERC and the netlist diff → append to `docs/rework-log-N.md` (symptom / root cause / fix; N = last verification round + 1) → set the issue `fixed-pending-verify`, **citing the rework-log entry in the same edit**.
Then assess cascading rework **before routing**: schematic changes may invalidate placement/routing — set each invalidated step to `rework` with a one-line reason. Route last: rework steps in order, then **step6-verify**, each in a fresh session.

## Wrap up
⛔ Gate: present the BOM (with rationale & ★flags) + ERC/netlist results for user confirmation. Mark step 3 `done`, tell the user: **new session, run **step4-placement** (Claude Code: `/boardless-pcb:step4-placement`)**.