Latency Adjusted Resource Equivalence

---
name: latency-adjusted-resource-equivalence
description: Probes the resource-latency trade-off between FPGA programmable logic (hls4ml) and AMD AI Engines for dense neural network layers. It quantifies the minimum PL hardware resources required to match AIE inference latency, identifying architectural crossover points for different layer shapes and reuse factors. Use when the user has predictions and gold and needs to compute LARE (Latency-Adjusted Resource Equivalence).
metadata:
  skill_kind: metric
  source_arxiv: 2604.19106
  bibtex_key: ma2026designrules
  confidence: high
---

# latency-adjusted-resource-equivalence

> Design Rules for Extreme-Edge Scientific Computing on AI Engines — Ma et al. (2026) (arXiv:2604.19106, 2026)

## What this evaluates

Probes the resource-latency trade-off between FPGA programmable logic (hls4ml) and AMD AI Engines for dense neural network layers. It quantifies the minimum PL hardware resources required to match AIE inference latency, identifying architectural crossover points for different layer shapes and reuse factors.

## Datasets

- **Synthetic Dense Layers** — total ?; splits: (unstated)

## Metrics

- `LARE (Latency-Adjusted Resource Equivalence)` **(primary)** — range: other (hardware resource units)
  - LARE is the minimum PL resource consumption ($R_{\mathrm{PL}}$) required for an hls4ml implementation to match the steady-state latency (Interval) of an AIE implementation for a given dense layer shape ($n_{\mathrm{in}}, n_{\mathrm{out}}$). It is computed by sweeping the PL reuse factor ($rf$), interpolating to find $rf_{\mathrm{eq}}$ where $P_{\mathrm{AIE}} = P_{\mathrm{PL}}(rf_{\mathrm{eq}})$, and evaluating $R_{\mathrm{PL}}$ at that $rf_{\mathrm{eq}}$.

## Input / output format

**Input**: Dense layer dimensions ($n_{\mathrm{in}}, n_{\mathrm{out}}$) and data type (e.g., i8×i8). For PL, a reuse factor ($rf$) is swept; for AIE, a naive 1-layer-per-tile mapping is assumed.

**Output**: LARE value (PL resource consumption at equivalence) and corresponding steady-state latency (Interval).

## Scoring recipe

```python
def compute_lare(n_in, n_out):
    P_aie = get_aie_latency(n_in, n_out)
    rf_eq = None
    for rf in legal_reuse_factors(n_in, n_out):
        P_pl = get_pl_latency(n_in, n_out, rf)
        if P_pl <= P_aie:
            rf_eq = interpolate_rf(n_in, n_out, P_aie)
            break
    if rf_eq is None:
        rf_eq = max_legal_rf(n_in, n_out)
    lare = get_pl_resources(n_in, n_out, rf_eq)
    return lare
```

## Common pitfalls

- Confusing the PL 'Latency' vs 'Resource' strategy; the paper explicitly uses the 'Resource' strategy as the baseline for fair comparison.
- Assuming LARE is a fixed constant per model; it varies non-linearly with layer shape ($n_{in}, n_{out}$) and is computed per layer, not per network.
- Ignoring that AIE performance here assumes a naive 1-layer-per-tile mapping, which underestimates AIE potential compared to optimized tiling.

## Evidence (verbatim from paper)

> We define the minimum PL resource required for hls4ml to match the AIE performance as the latency-adjusted resource equivalent (LARE), as shown in Algorithm 1. LARE identifies the crossover between the PL-favorable and AIE-favorable regimes for that layer shape.

## Citation

```bibtex
@misc{ma2026designrules,
  title={Design Rules for Extreme-Edge Scientific Computing on AI Engines},
  author={Ma et al. (2026)},
  year={2026},
  note={arXiv:2604.19106}
}
```

- arXiv: 2604.19106