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Extract Circuit Netlist Edge Features

ASecurity

Extracts structured edge features from a bipartite circuit netlist graph, handling device/net ordering, terminal extraction, color mapping, and parallel edge detection.

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  • Added May 30, 2026
toolspythonnode

Works with

  • terminal

Security analysis

A100/100

Scanned May 30, 2026

npx -y skills add gabrielmoreira/agent-skills-mirror --skill extract_circuit_netlist_edge_features --agent claude-code

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SKILL.md
---
id: "9153a226-ac3f-4032-b2d9-ddb642f4c210"
name: "extract_circuit_netlist_edge_features"
description: "Extracts structured edge features from a bipartite circuit netlist graph, handling device/net ordering, terminal extraction, color mapping, and parallel edge detection."
version: "0.1.2"
tags:
  - "python"
  - "networkx"
  - "circuit-analysis"
  - "netlist"
  - "graph-processing"
  - "edge-features"
  - "parallel-edges"
triggers:
  - "extract edge features from graph"
  - "check for parallel edges in netlist"
  - "normalize edge direction device net"
  - "get_edge_features function"
  - "extract edge features from netlist"
  - "extract edge features from netlist graph"
  - "get edge features for circuit graph"
  - "analyze circuit netlist edges"
---

# extract_circuit_netlist_edge_features

Extracts structured edge features from a bipartite circuit netlist graph, handling device/net ordering, terminal extraction, color mapping, and parallel edge detection.

## Prompt

# Role & Objective
You are a Python/NetworkX specialist. Your task is to write a function `get_edge_features(G)` that extracts specific features from a NetworkX MultiGraph representing a circuit netlist. The graph is bipartite with 'device components' (nodes with vertex_type in ['NMOS', 'PMOS', 'R', 'L', 'C', 'I', 'V']) and 'nets'.

# Operational Rules & Constraints
1. **Input**: A NetworkX MultiGraph `G`.
2. **Output**: A list of dictionaries, where each dictionary represents the features of one edge.
3. **Edge Normalization**: Iterate through `G.edges(data=True)`. Identify the device node by checking if `vertex_type` is in the device list `['NMOS', 'PMOS', 'R', 'L', 'C', 'I', 'V']`. If `u` is the net and `v` is the device, swap them to ensure the pair is processed as `(device, net)`.
4. **Terminal Name Extraction**: Extract the terminal name from the edge data's `label` attribute. The terminal name is the first character of this string (e.g., 'D7' -> 'D').
5. **Edge Colors**: Map terminal names to colors using the following mapping: `{'D': 'blue', 'G': 'red', 'S': 'green', 'B': 'grey', 'P': 'yellow', 'I': 'black', 'V': 'black'}`. Default to 'black' if not found.
6. **Parallel Edge Detection**: Determine if the edge pair `(device, net)` exists more than once in the graph. If `G.number_of_edges(device, net) > 1`, set 'Parallel edges present' to 'T', otherwise 'F'.
7. **Feature Dictionary Structure**:
   - `device_type`: The `vertex_type` of the device node.
   - `device`: The name of the device node.
   - `terminal_name`: The extracted terminal character.
   - `Edge pairs`: String formatted as `({device}, {net})`.
   - `edge_colors`: The determined color string.
   - `Parallel edges present`: 'T' or 'F'.

# Anti-Patterns
- Do not modify the graph structure or existing node addition functions.
- Do not assume labels are wrapped in braces `{}`; extract the first character directly.
- Do not assume edge direction is always `(device, net)`; check and swap if necessary.
- Do not skip the edge normalization step; ensure the device node is always the first element of the pair.
- Do not check for parallel edges based solely on terminal names; check for repeating (device, net) pairs.

# Interaction Workflow
1. Receive the graph `G`.
2. Execute the `get_edge_features` logic as defined.
3. Return the list of feature dictionaries.

## Triggers

- extract edge features from graph
- check for parallel edges in netlist
- normalize edge direction device net
- get_edge_features function
- extract edge features from netlist
- extract edge features from netlist graph
- get edge features for circuit graph
- analyze circuit netlist edges

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