Claude Skills by fireostendere

Complete headless DipTrace board build pipeline extracted from proven builds (attiny85-arduino-clone 3772 LOC + i2c-level-shifter 532 LOC + dut-controller-reva). Covers LCSC sourcing → schematic generation → visual wiring → nativeize → PCB placement/routing → pours/silk → SVG preview → native DRC verification. Use when building any new board.

Choose and implement the grounding strategy of a DipTrace PCB — continuous polygon vs star tie vs islands — from datasheet evidence, and build it headless with pours, stitching vias and thermal reliefs. Use when starting a PCB layout, placing a switching regulator or QFN part, or reviewing a ground system.

Plan and place physical PCB test points (standalone probe pads) on a DipTrace board through the DipTrace MCP server — coverage audit, free-grid candidate selection, guarded dry-run placement, stub routing, and post-checks. Use when the user asks to add or place testpoints on a PCB, improve probe access or testability, plan fixture/bed-of-nails points, or audit PCB test-point coverage.

Create or edit readable DipTrace schematics and multi-sheet overview diagrams while preserving verified library parts, page containment, and clear human-oriented wiring. Use for schematic authoring or visual cleanup, not read-only electrical review.

Fetch real LCSC/EasyEDA component catalog data over plain HTTPS: resolve an MPN to its LCSC part code, download the combined symbol+footprint JSON from the EasyEDA API, grab the official datasheet PDF, and convert the geometry into a DipTrace .elixml library fragment for schematic/PCB builds. Use when the user asks to source parts, download a datasheet, get a component symbol or footprint from EasyEDA/LCSC/JLCPCB, or feed vendor geometry into the headless DipTrace build pipeline. Not for the ...

Quick-reference card for all ponytail modes, skills, and commands. One-shot display, not a persistent mode. Trigger: /ponytail-help, "ponytail help", "what ponytail commands", "how do I use ponytail".

Code review focused exclusively on over-engineering. Finds what to delete: reinvented standard library, unneeded dependencies, speculative abstractions, dead flexibility. One line per finding: location, what to cut, what replaces it. Use when the user says "review for over-engineering", "what can we delete", "is this over-engineered", "simplify review", or invokes /ponytail-review. Complements correctness-focused review, this one only hunts complexity.

Project-authored guidance for DipTrace XML parser, writer, review and evidence work; preserve unknowns and separate synthetic observations from live evidence.

RAG-backed. Plan and optionally commit one bounded critical-net or differential-pair route in DipTrace with explicit rules and post-checks. Use when the user says “Route this explicitly named critical PCB net.”

RAG-backed. Plan or guide first power-on, programming, measurements, functional acceptance, and repeatable production tests for a specific DipTrace board revision. Use for assembled boards, bring-up, fixture plans, or production test procedures; «первое включение», «проверка собранной платы». Use when the user says “Plan or run bring-up for this DipTrace board.”

RAG-backed. Build and check a purchasable DipTrace BOM for a specified assembly variant and quantity, verify live stock, and assess substitutions. Use for BOM completeness, component sourcing, JLCPCB/LCSC selection, shortages, or procurement preparation; «подбери компоненты», «проверь BOM». Use when the user says “Prepare a purchasable BOM for this DipTrace revision.”

RAG-backed. Extract auditable schematic, package, footprint, and PCB layout requirements from official component documents into project rules. Use before choosing or placing physical parts, checking a pin map, or resolving component-specific requirements; «требования из даташита». Use when the user says “Extract official component rules for this DipTrace design.”

RAG-backed. Collect reviewable DipTrace evidence with native headless PCB acceptance when supported, open/save/close for all four editors and supported native capture; for unsupported actions guide an operator through quarantined source/open-save/re-export capture, dry-run ingest, MCP validation, explicit confirmation, and metadata recording. Use when the user says “Guide an operator through a reviewable DipTrace round-trip capture.”

RAG-backed. Prepare and inspect a versioned DipTrace fabrication and assembly package with real native CAM files, reconciled BOM/CPL, production instructions, and release evidence. Use for Gerber/NC Drill, assembly files, JLCPCB handoff, or a fabrication release; «файлы на производство». Use when the user says “Prepare this DipTrace board for fabrication and assembly.”

RAG-backed. Compare DipTrace hardware revisions, trace electrical/BOM/layout changes, and prepare an ECO with affected verification and release artifacts. Use for netlist diffs, substitutions, rework reconciliation, design regressions, or a new board revision; «сравни ревизии», «ECO платы». Use when the user says “Compare these DipTrace revisions and prepare an ECO.”

RAG-backed. Audit DipTrace component and pattern libraries for pin, pad, mapping, geometry, and identity defects without mutating native libraries. Use when the user says “Audit these DipTrace component and pattern libraries.”

RAG-backed. Take a DipTrace board through requirements, source evidence, schematic, PCB, production handoff, bring-up, and revisions using existing project skills and explicit build gates. Use for a full design cycle, a new board specification, or resuming a PCB build; «полный цикл платы», «ТЗ на плату», «продолжи разработку». Use when the user says “Take this board through the complete design and production cycle.”

RAG-backed. Inventory a bounded DipTrace project, its document identity, models, rules, connectivity, unknowns, and evidence before planning changes. Use when the user says “Inventory this DipTrace project before we plan work.”

RAG-backed. Produce an explicit evidence-based PASS or BLOCKED decision from implemented DipTrace review profiles and disclosed missing checks. Use when the user says “Run the final evidence-based release gate for this design.”

RAG-backed. Design, build, modify, and review electronic devices and schematics through DipTrace MCP with source-backed engineering decisions. Use for architecture, schematic capture, and engineering review; coordinate PCB and production work through pcb-design-workflow when requested. Use when the user says “Design or modify this DipTrace schematic.”

RAG-backed. Review a DipTrace schematic with bounded ERC, logical connectivity, metadata, and BOM checks before layout. Use when the user says “Review this DipTrace schematic before layout.”

RAG-backed. Review DipTrace PCB impedance, stackup, routed geometry, return paths, and configured external-solver evidence without inventing targets. Use when the user says “Review impedance and return-path evidence for these PCB nets.”

RAG-backed. Measure and improve explicit standalone-pad testpoint coverage through a guarded DipTrace PCB transaction. Use when the user says “Plan guarded fixture testpoints for these PCB nets.”