Sub Bit Snn Compression

---
name: sub-bit-snn-compression
version: v1.0.0
last_updated: 2026-05-05
description: Sub-bit quantization techniques for spiking neural networks to further reduce storage and computation beyond binary SNNs. Based on NeurIPS 2025 S2NN paper.
---

# Sub-bit SNN Compression

Compress spiking neural networks below 1-bit per parameter using sub-bit quantization techniques for ultra-efficient deployment on resource-constrained hardware.

## Source Paper

- **Title:** S2NN: Sub-bit Spiking Neural Networks
- **Venue:** NeurIPS 2025
- **Key Insight:** Despite binary SNN advances, storage and computation demands remain substantial for large-scale networks. Sub-bit encoding further compresses SNN parameters below 1-bit while maintaining accuracy through structured sparsity and temporal redundancy exploitation.

## Activation Keywords

- sub-bit SNN
- SNN compression
- spiking neural network quantization
- ultra-low-bit SNN
- S2NN
- SNN 亚比特压缩
- 脉冲神经网络压缩

## Core Methodology

### Key Techniques

1. **Temporal Redundancy Exploitation**
   - SNN spikes are sparse in time
   - Encode repeated spike patterns with fewer bits
   - Use run-length or dictionary coding for spike trains

2. **Structured Sparsity**
   - Identify redundant connections in trained SNNs
   - Apply sub-bit encoding to sparse weight matrices
   - Maintain accuracy through importance-aware pruning

3. **Sub-bit Parameter Encoding**
   - Below 1-bit per weight compression
   - Shared codebooks for weight clusters
   - Temporal coding leverages spike event sparsity

### Workflow

1. Train standard SNN with surrogate gradient
2. Analyze spike sparsity patterns across timesteps
3. Apply structured pruning based on connection importance
4. Encode remaining parameters using sub-bit codebook
5. Deploy compressed model on target hardware

## Application Scenarios

1. Edge device deployment: microcontrollers, IoT sensors
2. Large-scale SNN: reduce memory footprint for deep SNNs
3. Neuromorphic hardware: match hardware precision constraints
4. Real-time inference: minimize memory bandwidth requirements

## Implementation Considerations

- Trade-off between compression ratio and accuracy
- Hardware support for sub-bit operations
- Decoding overhead during inference
- Calibration data for codebook optimization

## Pitfalls

1. Accuracy drops significantly if compression too aggressive
2. Decoding latency may negate computation savings
3. Requires careful calibration of codebook sizes
4. Not all SNN architectures benefit equally

## Related Skills

- quantized-snn-hardware-optimization
- snn-performance-analysis
- snn-quantized-dynamics-integer